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As a Physical Implementation, you will play a crucial role in the design and implementation of cutting-edge ASICs and SOC solutions. The successful candidate will be responsible for:

• Utilize industry-standard tools such as DC or DCG for efficient design synthesis.
• Proficient in creating and debugging SDC (Synopsys Design Constraints) files.
• Develop layout guidelines to ensure optimal timing and performance.
• Possess expertise in static timing analysis (STA) to validate and optimize designs.
• Ensure adherence to timing closure requirements and perform other STA signoff checks.
• Demonstrate a high level of technical proficiency to implement both Chip top and Block level designs.
• Identify and address issues in the design flow, striving for continuous improvement.

Requirements:

• Minimum 8 years of experience in Physical Implementation.
• Experience in design synthesis by DC or DCG, SDC making & debug 
• Experience in layout guidelines, and static timing analysis.
• Strong technical skills in implementing both Chip top and Block level designs.
• Excellent interpersonal skills and analytical mindset, problem-solving, and decision-making abilities.
• Proficiency in English, both written and verbal.

• Competitive Salary Package (Basic salary + Retention bonus + Allowances...)
• 13th month salary, Tet Bonus, Profit share, Long-term Bonus…
• Working model: working at the office (Flexible time)
• Company trip, Workshop, Team Building…
• Social insurance (full salary), Annual Health check, PTI healthcare for employees & family
• Annual leave 15 days/year, birthday /holiday party…