[JAPAN] Backend Design Engineer

freeC's Client

Image sensor back-end operations

• Logic layout (P & R) process:

Floorplan, place and route, CTS, physical verification (DRC / LVS), and results analysis/improvement / correction corresponding to them

• Chip top layout, physical verification:

Floor plan, place and route, physical verification (DRC / LVS), power supply network analysis, and results analysis/improvement / correction associated with them

• Logic synthesis, timing verification (MD) process:

Logic synthesis, equivalence verification, SDC creation, STA, power consumption calculation, and accompanying result analysis/improvement / correction support Necessary technical skills

Must have (one of the following):

• Logic layout (P & R) process

Work experience: Design experience using P & R tools (image sensor, SoC etc)

• Chip top layout, physical verification

Work experience: Design experience using manual layout tools (image sensor, SoC, Memory, etc)

• Logic synthesis, timing verification (MD) process

Work experience: Design experience using EDA tools (logic synthesis or SDC creation or STA)

Nice to have:

• Logic layout (P & R) process: IC-Compiler II, Formality, StarRC, Caliber
• Chip top layout, physical verification: α-SX, SX-Meistar, Caliber, RedHawk
• Logic synthesis, timing verification (MD) Process: DesignCompiler, Formality, PrimeTime-SI, PrimeTime-ECO, PrimeTime-PX