Senior Design Verification Engineers (VLSI)

freeC's Client

• Leading the development and modification of full chip test plans to ensure comprehensive verification coverage.
• Designing and modifying testbenches to facilitate efficient verification.
• Developing, coding, executing, and analyzing test cases to identify and resolve bugs.
• Conducting regressions and coverage analysis to track verification progress and identify areas for improvement.
• Driving verification closure activities to ensure the project meets quality standards.
• Ensuring process compliance within the assigned module and actively participating in technical discussions and reviews.
• Preparing and submitting detailed status reports to mitigate project risks and address escalations effectively.

Required Skills and Experiences:

• Bachelor's or Master’s degree in Electronics/Electrical Engineering with at least 5 years of experience in verification.
• Intermediate English with the ability to communicate at basic level.
• Strong understanding of the ASIC/SoC life cycle.
• Extensive experience in full chip test plan development and modification.
• Proficiency in testbench development/modification, test case development, coding, execution, bug analysis, regressions, coverage analysis, and verification closure.
• Experience with gate-level simulations.
• Proficiency in scripting languages.
• Involvement in multiple ASIC/SoC verifications up to the tape-out stage.
• Excellent English communication skills for effective working communication.

- 18 paid leaves/year (12 annual leaves and 6 personal leaves)

- Insurance plan based on full salary + 13th month salary + Performance bonus

- Meal allowance of 730,000 VND/month

- 100% full salary and benefits as an official employee from the 1st day of working

- Medical benefit for employee and family

- Working in a fast-paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries)

- Internal training (Technical & Functional & English)