29 new jobs

• Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing;
• Support STA timing analysis and fixing;
• Perform physical verification, including DRC, LVS, IR drop and DFM analysis.

Job Requirement

• Graduated with Bachelor degree of Electrical Engineer/ Computer Science
• Have min 3+ years of experience as a Physical Design/ Chip Design
• Familiar with Cadence Innovus or Synopsys ICC2/ Fusion Compiler;
• English: Intermdiate level & above (TOEIC 730-855 is preferred;) to work with foreign Technical Manager and teammates
• Have experience in 65/40/28 nm IC design experiences will be plus;

• Bonus: 13th month of fixed bonus
• Incentive/performance bonus: 14th, 15th month salary (based on performance)
• Annual leave: 15 days/ year + 3 sick-leave
• Allowance: transportation allowance (1,5mil) + meal allowance (1,5mil)
• Insurance according to the Labor law based of full salary
• Probation: 2 months with 100% salary + PVI Healthcare insurance for the employee
• PVI Healthcare insurance for the employee + family members
• Annual company trip
• Annual salary review (each March)
• Year-end parties, birthday gifts,...
• Sign on bounus for Senior and Manager (from 5 years of experience or more.): 2 years commitment is required. After passing probation, offering signed Bonus equivalent to 3 times of based salary.
• Supportive policy: Internal transfer to Taiwan (if any)
• Business trip (if any): all costs are covered by the company + business trip allowance: 1,2mil/day