ASIC Verification Lead

freeC's Client

• Technically leads an SOC DV team and owns the delivery of a bug free complex SOC by working closely with Architecture, Systems and Design teams.
• Develops pre-silicon verification tests to verify system meet design requirements. Test generation, coverage improvement, post silicon debug, vector simulation.
• Well versed with UVM. Need to build testbench with monitors, checkers, scoreboard, etc as necessary. IP, Subsystem and SOC validation consultations. Bring up and guide DFT teams on DFT validation.
• Creates test plans for RTL validation, defines and runs system simulation models, finds and implements corrective measures for failing RTL tests.
• Analyses and uses results to modify testing methodology. Drives verification completion and RTL freeze decisions. Mentors juniors and teams when needed.

Must have:

• Proficiency in logic verification, processor-based verification and AMS verification.
• Proficiency in test architecture and test environment development, need to build testbench and implement monitors, checkers, scoreboard as necessary
• Simulation and debug of RTL/PA-RTL/GLS/PA-GLS
• Expertise in test planning, creating direct tests. Plan test scenarios and implement tests using SV/UVM/SVA/OVM/eRM/C-based verification. Hands on experience in constrained random, coverage driven verification methodologies. Well-versed with UVM validation methodology.
• Randomization, regression test planning and development, creating and executing verification strategy to monitor regression result and extract key parameters
• Proficiency in either IP level verification (protocol verification) or SOC-level verification
• Experience in mixed signal verification; developing AMS testbench, behavioral models for analog blocks
• Deep understanding of code coverage, functional coverage, assertions, cover groups etc and application of same to achieve 100% verification completeness prior to tape-out
• Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM
• Experience on UPF/CPF; verification of power intent, power up/down sequences.
• Experience with debug on simulators like VCS, NC-Verilog, Xcelium, Modelsim, etc.
• Mentoring of juniors and teams.
• Excellent analytical and debugging skills
• Architecture and verification knowledge of bus protocols like – AXI, AHB, APB, OCP and protocols like DDR/LPDDR, PCIe, USB, Ethernet, etc
• Understanding of PHYs like SERDES PHY, DDR/LPDDR PHYs
• Proficiency in any scripting language like Perl, Python, Shell/Tcl

Good to have one or more of following areas:

• Expertise in Low power verification
• Experience in performance validation
• Experience in verification support to post silicon bring up
• Experience in DFT test patterns validation

Experience range – 8- 15 years

• Attractive salary + 13th month salary
• 80% salary in probation
• Social insurance and other insurance in accordance with Vietnamese Labour Code
• Full insurance according to the law and other types of insurance on business trips
• Opportunity to join training courses
• Professional, dynamic and creative environment. Colleagues are sociable, happy, always support new recruits
• Salary review annually at the end of the year