ASIC PD Lead

freeC's Client

• Leads the physical design and physical verification (LVS, DRC) of a state-of-the-art SOC by working closely with front end design team, analog design team and Synth/STA team.
• Works with execution driven teams for tape-outs by supporting new flows and new methodologies needed to address better QoR through better meeting of PPA goals.
• Must have in-depth understanding of ASIC design flow and experience on multiple tape-outs in deep sub-micron FinFET technologies.

Must have:

• Proficiency in RTLtoGDSII flows. Able to take any design through PnR flow to achieve PPA objectives. Should have driven multiple SOC tape-outs consistently across deep sub-micron process technologies.
• Proficiency in physical design tools such as ICC, Cadence Genus/Tempus/Voltus, etc
• Able to work with DC, PT, DCT, PTSI.
• Expertise in timing closure working with front end design teams and STA teams. Deep understanding of PVT corners. Able to achieve timing closure while meeting power and area goals.
• Expertise in floorplanning to meet PPA objectives at block, subsystem and chip level.
• Experience in and understanding of signal integrity/crosstalk checks
• Expertise in implementing functional and timing ECOs
• Expertise in low power implementation of physical design. Proficiency in understanding of power structures, building of power islands and implementing necessary isolation /retention strategies. Expertise in IR drop analysis. Will work with package teams for high quality power delivery and PDN performance.
• Expertise in scan insertion and working with DFT team to implement scan stitching, scan compression and decompression, and test point insertions as per the DFT strategy
• Experience in DFM and DFY for deep submicron technologies
• Excellent understanding and expertise in LVS, DRC, Antenna, EM/IR drop, etc in deep submicron technologies.
• SDF creation for GLS and parasitic extraction as per different parasitic rules.
• Proficiency in one or more scripting language like C, Perl, Python, Shell, Tcl

Good to have:

• Experience in planning bump placement/ ball placement, power and ground bumps, IO structures and pad placements is useful.
• Good understanding of flow implementation. Should have driven process automation in one or more steps from floorplanning, clock tree synthesis, improved place and route techniques, timing closure, power mesh implementation, guard ring and other noise removal structures, scan stitch flow, etc.
• Deep understanding of LVS, DRC, Antenna, DFM, DFY rule decks and how they impact functionality/parametrics.
• Deep understanding of design parasitics and how they impact design functionality and parametrics.

Experience range – 8- 15 years

• Attractive salary + 13th month salary
• 80% salary in probation
• Social insurance and other insurance in accordance with Vietnamese Labour Code
• Full insurance according to the law and other types of insurance on business trips
• Opportunity to join training courses
• Professional, dynamic and creative environment. Colleagues are sociable, happy, always support new recruits
• Salary review annually at the end of the year