ASIC DFT Lead

freeC's Client

• DFT Lead. Develops and supports DFT (design for test) structures, determines approaches for DFT and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital (scan & logic BIST) and analog circuitry (analog BIST).
• Performs scan synthesis and cleans up any scan DRC violations. Creates, simulates and verifies ATPG patterns. Writes functional tests, MBIST, LBIST and other BIST patterns, simulates and verifies them. Has knowledge of various fault models.
• Plans and develops test patterns to find them in production test. Achieves maximum test and fault coverage in minimum test time. Supports test pattern bring up on tester, performs diagnosis of failing patterns on silicon and optimizes test time.
• Leads the DFT planning and execution on a state-of-the-art SOC by working closely with front end design team, Synth/STA team and physical design team. Supports new methodologies and flows to meet all testability goals. Aware of DFT flows, requirements, tools, processes and DFT standards. Participates in driving new DFT methodology and solutions to improve quality, reliability and in system test and debug capability.

Must have:

• Deep understanding and proficiency in Scan methodology, scan architecture, scan DRC and scan structures (scan flops, compress/decompress, etc). Proficiency in MBIST, JTAG, BSCAN structures, flows and test patterns.
• Proficiency in DFT tools such as Cadence Modus/Genus/Innovus, Mentor TestKompress, Synopsys DFT Compiler, etc
• Proficiency in RTL DV, GLS and PA-GLS. Proficiency in Verilog, System Verilog and simulator tools.
• Expertise in test architecture definition, including scan architecture, MBIST, LBIST, analog functional tests (for PLL etc), JTAG, BSCAN architecture.
• Expertise in implementing DFT structures as per plan and taking the chip through ATPG, pattern simulations and silicon bring-up on tester to meet the required testability goals.
• Expertise in scan insertion and working with P&R team to fix scan DRC issues.
• Expertise in implementing MBIST, JTAG, BSCAN and analog functional test structures in design, expertise in coming up with related test patterns.
• Awareness of PnR flow steps. Good understanding of the steps that directly affect DFT QoR, ie, DFT synthesis, scan insertion and stitching, Test mode STA, timing on DFT paths, test mode LEC, and IR drop analysis in DFT circuits.
• Strong analytical and problem-solving skills. Excellent debugging and hands-on flow bring-up skills to bring up test mode setup and ATPG.
• Ability to communicate clearly to senior management and to customers and explain issues to them. Good mentoring of juniors and other team members.
• Excellent understanding of different fault models like stuck-at, transition, bridging, IDDQ, etc and patterns to catch them
• Proficiency in one or more scripting language like C, Perl, Python, Shell, Tcl
• Awareness and knowledge of DFT standards like in Automotive (AEC-Q100, ISO 26262, AEC-Q004, etc), any other such DFT standards.

Good to have:

• Knowledge of advanced fault models
• Expertise in low power implementation of DFT.
• Good to have driven flow automation in DFT.

Experience range – 8- 15 years in DFT

• Attractive salary + 13th month salary
• 80% salary in probation
• Social insurance and other insurance in accordance with Vietnamese Labour Code
• Full insurance according to the law and other types of insurance on business trips
• Opportunity to join training courses
• Professional, dynamic and creative environment. Colleagues are sociable, happy, always support new recruits
• Salary review annually at the end of the year