ASIC Design and Verification Mentor

HCL GUVI

Job Description:

We are seeking a highly skilled and motivated ASIC Design and Verification Engineer to join our dynamic

team. The successful candidate will be responsible for designing, implementing, and verifying complex

ASIC designs for cutting-edge semiconductor products. This role requires expertise in digital design,

verification methodologies, and proficiency in scripting and programming languages. Additionally, the

candidate should possess strong problem-solving skills and the ability to work effectively in a

collaborative environment.

Responsibilities:

● Architect and implement digital ASIC designs meeting performance, power, and area

requirements.

● Develop and execute verification plans using industry-standard methodologies such as UVM

(Universal Verification Methodology).

● Write and debug RTL (Register Transfer Level) code in Verilog/SystemVerilog.

● Create and maintain verification environments, including testbenches, models, and functional

coverage.

● Collaborate with cross-functional teams including physical design, software, and validation to

ensure successful tape-out.

● Analyze and debug simulation failures and work closely with design teams to resolve issues.

● Participate in design reviews, providing feedback and guidance to improve design quality and

efficiency.

● Stay current with industry trends and advancements in ASIC design and verification

methodologies.