Position: Sr. SOC Verification Engineer
Required experience: 3+ to 7+ years
- Responsibilities:
- Committed and passionate about technical work
- Should be able to work independently and able to guide others
- The role requires this person to be the point of contact for handling and resolving technical queries for other engineers in the team.
Requirement:
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, test vector creation, simulations, gate level simulations
- Hands-on with System Verilog and Assertion-based verification methodology
- At least 3 years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Simulation Tools:
- NCSIM/VCS/ModelSim/Questa
- Added Advantage:
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF)
- Experience on System C
- Worked on protocols like AMBA, AHB/AXI, MIPI, PCI Express, SATA, USB.
Location: Hochiminh city