ASIC Design Senior

freeC's Client

• Senior member of architecture and design team.
• Works on block micro-architecture, coding synthesizable RTL and writing constraints for synthesis.
• Analyses 3rd party IP specs and translates to chip level specifications.

Must have:

• Proficiency in logic design, micro-architecture development
• Experience in SOC integration, IP integration
• Expertise in RTL implementation using Verilog, System Verilog
• Experience in protocols like – AXI, AHB, APB, OCP etc
• Good analytical and debug skills
• Experience in implementing power intent using UPF/CPF
• Expertise in Lint, CDC and Low power static verification

Good to have:

• Proficiency in any scripting language like Perl, Python, Shell/Tcl
• Experience in synthesis, LEC, support to STA and timing closure.
• Basic knowledge on DFT concepts like – SCAN, JTAG, MBIST
• Experience in DDR/LPDDR, PCIe, USB, Ethernet

Experience range – 4- 8 years

• Attractive salary + 13th month salary
• 80% salary in probation
• Social insurance and other insurance in accordance with Vietnamese Labour Code
• Full insurance according to the law and other types of insurance on business trips
• Opportunity to join training courses
• Professional, dynamic and creative environment. Colleagues are sociable, happy, always support new recruits
• Salary review annually at the end of the year